1. Field of the Invention
The present invention generally relates to an integrated circuit structure and a manufacturing method thereof, more particularly, to an interconnect-related integrated circuit structure and manufacturing method thereof.
2. Description of Related Art
In deep sub-micro integrated circuit technology, high-speed, multi-function, highly integrated, low power consumption and low cost ultra large scale integrated circuit chips are mass-produced as a result of the continuous reduction of device line width. Because of the miniaturization and the increase in the integration of devices, the density of interconnects also increases and leads to a jump in the resistance/capacitance (RC) of the devices. As a result, signal transmission or RC delay is increasingly important and the operating efficiency of the devices is lowered correspondingly.
To limit the effect caused by RC delay, low-k inter-layer dielectric layers are formed between the layers of multi-layer interconnects so as to reduce the parasitic capacitance between conductive wires, and the conductive wires are made of copper instead of aluminum so as to reduce electrical resistance. Therefore, the operating speed and performance of the device is enhanced.
However, the adhesion of a low-k dielectric layer and a silicon oxide dielectric layer is poor and the serious effect caused by dielectric peeling leads to the drop of particles and the bridging between metals from the subsequently copper interconnect process. Therefore, the probability of resulting in a short circuit between some of the copper wires is increased and the process yield can be adversely affected. In particular, when a larger stress is applied to a thermal stress test of a flip-chip package, dielectric peeling is easily induced so that the reliability of the device can be substantially reduced.